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DATA SHEET
MOS INTEGRATED CIRCUIT
PD64A, 65
4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROL TRANSMISSION
DESCRIPTION
Equipped with low-voltage 2.0 V operation, a carrier generation circuit for infrared remote control transmission, a standby release function through key entry, and a programmable timer, the PD64A and 65 are suitable for infrared remote control transmitters. For the PD64A and 65, we have made available the one-time PROM product PD6P5 (under development) for program evaluation or small-quantity production.
FEATURES
* Program memory (ROM) * PD64A : 1002 x 10 bits * PD65 : 2026 x 10 bits * Data memory (RAM) * 9-bit programmable timer * Command execution time * Stack level * I/O pins (KI/O) * Input pins (KI) * Sense input pin (S0, S2) * S1/LED pin (I/O) * Power supply voltage * Oscillator frequency * POC circuit : 32 x 4 bits : 1 channel : 16 s (when operating at fX = 4 MHz: ceramic oscillation) : 1 level (Stack RAM is for data memory RF as well.) : 8 units : 4 units : 2 units : 1 unit (When in output mode, this is the remote control transmission display pin.) : VDD = 2.0 to 3.6 V : fX = 2.4 to 8 MHz * Operating ambient temperature : TA = -40 to +85 C * Built-in carrier generation circuit for infrared remote control
APPLICATION
Infrared remote control transmitter (for AV and household electric appliances)
Unless otherwise specified, the PD65 is treated as the representative model throughout this document.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14380EJ2V0DS00 (2nd edition) Date Published November 1999 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1999
PD64A, 65
ORDERING INFORMATION
Part Number Package 20-pin plastic SSOP (300 mil) 20-pin plastic SSOP (300 mil)
PD64AMC-xxx-5A4 PD65MC-xxx-5A4
Remark xxx indicates ROM code suffix.
PIN CONFIGURATION (TOP VIEW)
20-pin Plastic SSOP (300 mil) * PD64AMC-xxx-5A4 * PD65MC-xxx-5A4
KI/O6 KI/O7 S0 S1/LED REM VDD XOUT XIN GND S2
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0
Caution The pin numbers of KI and KI/O are in the reverse order of the PD6600A, and 6124A.
2
Data Sheet U14380EJ2V0DS00
PD64A, 65
BLOCK DIAGRAM
REM
CARRIER GENERATOR
4 CPU CORE ROM 8
PORT KI
4
KI0-KI3
PORT KI/O
8
KI/O0-KI/O7
S1/LED
9-bit TIMER
3
PORT S
3
S0, S1/LED, S2
RAM
SYSTEM CONTROL
XIN XOUT VDD GND
LIST OF FUNCTIONS
Item ROM capacity
PD64A
1002 x 10 bits Mask ROM 32 x 4 bits 1 level (multiplexed with RF of RAM) * * * *
PD65
2026 x 10 bits
PD6P5
One-time PROM
RAM capacity Stack I/O pins
Key input (KI) Key I/O (KI/O) Key extended input (S0, S1, S2) Remote control transmission display output (LED)
: : : :
4 8 3 1 (multiplexed with S1 pin)
Number of keys Clock frequency Instruction execution time Carrier frequency Timer POC circuit Supply voltage Operating ambient temperature Package
* 32 keys * 56 keys (when extended by key extension input) Ceramic oscillation * fX = 2.4 to 8 MHz 16 s (fX = 4 MHz) fX/8, fX/16, fX/64, fX/96, fX/128, fX/192, no carrier (high level) 9-bit programmable timer: 1 channel Internal VDD = 2.0 to 3.6 V TA = -40 to +85 C 20-pin plastic SSOP (300 mil) Ceramic oscillation * fX = 2.4 to 5.6 MHz
Data Sheet U14380EJ2V0DS00
3
PD64A, 65
CONTENTS 1. PIN FUNCTIONS ...............................................................................................................................
1.1 1.2 1.3 List of Pin Functions ............................................................................................................................... INPUT/OUTPUT Circuits of Pins ............................................................................................................ Dealing with Unused Pins ......................................................................................................................
6
6 7 8
2. INTERNAL CPU FUNCTIONS ..........................................................................................................
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Program Counter (PC) ............................................................................................................................ Stack Pointer (SP) ................................................................................................................................... Address Stack Register (ASR (RF)) .......................................................................................................
9
9 9 9
Program Memory (ROM) ......................................................................................................................... 10 Data Memory (RAM) ................................................................................................................................ 10 Data Pointer (DP) ..................................................................................................................................... 11 Accumulator (A) ...................................................................................................................................... 11 Arithmetic and Logic Unit (ALU) ............................................................................................................ 12 Flags ......................................................................................................................................................... 12 2.9.1 2.9.2 Status flag (F) ............................................................................................................................... 12 Carry flag (CY) ............................................................................................................................. 13
3. PORT REGISTERS (PX) ................................................................................................................... 14
3.1 3.2 KI/O Port (P0) ............................................................................................................................................. 15 KI Port/Special Ports (P1) ....................................................................................................................... 16 3.2.1 3.2.2 3.2.3 3.2.4 3.3 3.4 KI port (P11: bits 4-7 of P1) ........................................................................................................... 16 S0 port (bit 2 of P1) ....................................................................................................................... 16 S1/LED (bit 3 of P1) ...................................................................................................................... 16 S2 port (bit 1 of P1) ....................................................................................................................... 17
Control Register 0 (P3) ........................................................................................................................... 17 Control Register 1 (P4) ........................................................................................................................... 18
4. TIMER ............................................................................................................................................... 19
4.1 4.2 4.3 4.4 Timer Configuration ................................................................................................................................ 19 Timer Operation ....................................................................................................................................... 20 Carrier Output .......................................................................................................................................... 21 Software Control of Timer Output ......................................................................................................... 21
5. STANDBY FUNCTION ...................................................................................................................... 22
5.1 5.2 5.3 Outline of Standby Function .................................................................................................................. 22 Standby Mode Setup and Release ......................................................................................................... 23 Standby Mode Release Timing .............................................................................................................. 25
6. RESET ............................................................................................................................................... 26 7. POC CIRCUIT ................................................................................................................................... 27
7.1 7.2 Functions of POC Circuit ........................................................................................................................ 28 Oscillation Check at Low Supply Voltage ............................................................................................. 28
8. SYSTEM CLOCK OSCILLATOR ...................................................................................................... 29
4
Data Sheet U14380EJ2V0DS00
PD64A, 65
9. INSTRUCTION SET .......................................................................................................................... 30
9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Machine Language Output by Assembler ............................................................................................. 30 Circuit Symbol Description .................................................................................................................... 31 Mnemonic to/from Machine Language (Assembler Output) Contrast Table ..................................... 32 Accumulator Operation Instructions ..................................................................................................... 36 Input/Output Instructions ....................................................................................................................... 39 Data Transfer Instructions ...................................................................................................................... 40 Branch Instructions ................................................................................................................................ 42 Subroutine Instructions .......................................................................................................................... 43 Timer Operation Instructions ................................................................................................................. 44
9.10 Others ....................................................................................................................................................... 45
10. ASSEMBLER RESERVED WORDS ................................................................................................ 47
10.1 Mask Option Directives ........................................................................................................................... 47 10.1.1 OPTION and ENDOP directives .................................................................................................. 47 10.1.2 Mask option definition directive .................................................................................................... 47
11. ELECTRICAL SPECIFICATIONS ..................................................................................................... 48 12. CHARACTERISTIC CURVE (REFERENCE VALUES) .................................................................... 52 13. APPLIED CIRCUIT EXAMPLE ......................................................................................................... 53 14. PACKAGE DRAWINGS .................................................................................................................... 54 15. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 55 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................... 56 APPENDIX B. FUNCTIONAL COMPARISON BETWEEN PD64A, 65 AND OTHER PRODUCTS .... 57 APPENDIX C. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT ................................ 58
Data Sheet U14380EJ2V0DS00
5
PD64A, 65
1. PIN FUNCTIONS 1.1 List of Pin Functions
Pin No. 1 2 15-20 Symbol KI/O0-KI/O7 Function These pins refer to the 8-bit I/O ports. I/O switching can be made in 8-bit units. In INPUT mode, a pull-down resistor is added. In OUTPUT mode, they can be used as a key scan output from key matrix. Refers to the input port. Can also be used as a key return input from key matrix. In INPUT mode, the availability of the pull-down resistor of the S0 and S1 ports can be specified by software in terms in 2-bit units. If INPUT mode is canceled by software, this pin is placed in OFF mode and enters the high-impedance state. 4 S1/LED Refers to the I/O port. In INPUT mode (S1), this pin can also be used as a key return input from key matrix. The availability of the pull-down resistor of the S0 and S1 ports can be specified by software in 2-bit units. In OUTPUT mode (LED), this pin becomes the remote control transmission display output (active low). When the remote control carrier is output from the REM output, this pin outputs the low level from the LED output synchronously with the REM signal. Refers to the infrared remote control transmission output. The output is active high. Carrier frequency: fX/8, fX/64, fX/96, high-level, fX/16, fX/128, fX/192 (usable on software) 6 7 8 9 10 VDD XOUT XIN GND S2 Refers to the power supply. These pins are connected to system clock ceramic resonators. Refers to the ground. Refers to the input port. The use of the STOP mode release of the S2 port can be specified by software. When using this pin as a key input from a key matrix, enable the use of the STOP mode release (at this time, a pull-down resistor is connected internally.) When the STOP mode release is disabled, this pin can be used as the input port which does not release the STOP mode even if the release condition is established (at this time, a pull-down resistor is not connected internally.) 11-14 KI0-KI3Note 2 These pins refer to the 4-bit input ports. They can be used as a key return input from key matrix. The use of the pull-down resistor can be specified by software in 4-bit units. -- Input (low-level) -- -- -- -- -- Low level (oscillation stopped) -- Input (high-impedance, STOP mode release cannot be used) CMOS push-pull High-level output (LED) Output Format CMOS push-pullNote 1 When Reset High-level output
3
S0
--
High-impedance (OFF mode)
5
REM
CMOS push-pull
Low-level output
Notes 1. Be careful about this because the drive capability of the low-level output side is held low. 2. In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when POC is released due to supply voltage startup.
6
Data Sheet U14380EJ2V0DS00
PD64A, 65
1.2 INPUT/OUTPUT Circuits of Pins
The input/output circuits of the PD64A and 65 pins are shown in partially simplified forms below. (1) KI/O0-KI/O7
VDD data Output latch
(4) S0
Input buffer
P-ch
OFF mode
output disable Selector N-chNote
standby release
Input buffer
pull-down flag
N-ch
N-ch
(5) S1/LED Note The drive capability is held low. (2) KI0-KI3
standby release Input buffer
REM output latch VDD
P-ch
output disable standby release Input buffer
N-ch
pull-down flag
N-ch
pull-down flag N-ch
(3) REM
(6) S2
standby release Input buffer
P-ch
VDD
data
Output latch N-ch
Carrier generator
STOP release ON/OFF
N-ch
Data Sheet U14380EJ2V0DS00
7
PD64A, 65
1.3 Dealing with Unused Pins
The following connections are recommended for unused pins. Table 1-1. Connections for Unused Pins
Connection Inside the microcontroller KI/O INPUT mode OUTPUT mode REM S1/LED S0 S2 K1 -- High-level output -- OUTPUT mode (LED) setting OFF mode setting -- -- Directly connect these pins to GND Outside the microcontroller Leave open
Pin
Caution The I/O mode and the terminal output level are recommended to be fixed by setting them repeatedly in each loop of the program.
8
Data Sheet U14380EJ2V0DS00
PD64A, 65
2. INTERNAL CPU FUNCTIONS 2.1 Program Counter (PC): 11 Bits
Refers to the binary counter that holds the address information of the program memory. Figure 2-1. Program Counter Organization
PC
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
The program counter contains the address of the instruction that should be executed next. Normally, the counter contents are automatically incremented in accordance with the instruction length (byte count) each time an instruction is executed. However, when executing JUMP instructions (JMP, JC, JNC, JF, JNF), the program counter contains the jump destination address written in the operand. When executing the subroutine call instruction (CALL), the call destination address written in the operand is entered in the PC after the PC contents at the time are saved in the address stack register (ASR). If the return instruction (RET) is executed after the CALL instruction is executed, the address saved in the ASR is restored to the PC. When reset, the value of the program counter becomes "000H".
2.2 Stack Pointer (SP): 1 Bit
Refers to the 1-bit register which holds the status of the address stack register. The stack pointer contents are incremented when the call instruction (CALL) is executed; they are decremented when the return instruction (RET) is executed. When reset, the stack pointer contents are cleared to "0". When the stack pointer overflows (stack level 2 or more) or underflows, the CPU is hung up thus a system reset signal is generated and the PC becoming "000H". As no instruction is available to set a value directly for the stack pointer, it is not possible to operate the pointer by means of a program.
2.3 Address Stack Register (ASR (RF)): 11 Bits
The address stack register saves the return address of the program after a subroutine call instruction is executed. The low-order 8 bits are arranged in the RF of the data memory as a dual-function RAM. The register holds the ASR value even after the RET is executed. When reset, it holds the previous data (undefined when turning on the power). Caution If the RF is accessed as the data memory, the high-order 3 bits of the ASR become undefined. Figure 2-2. Address Stack Register Organization
RF ASR ASR10 ASR9 ASR8 ASR7 ASR6 ASR5 ASR4 ASR3 ASR2 ASR1 ASR0
Data Sheet U14380EJ2V0DS00
9
PD64A, 65
2.4 Program Memory (ROM): 1002 steps x 10 bits (PD64A) 2026 steps x 10 bits (PD65)
The ROM consists of 10 bits per step, and is addressed by the program counter. The program memory stores programs and table data, etc. The 22 steps from 7EAH to 7FFH cannot be used in the test program area. Figure 2-3.
(a) PD64A
Program Memory Map
(b) PD65
10 bits 000H 000H
10 bits
Page 0
Page 0
3E9H 3EAH
3FFH 400H
Unmounted areaNote Page 1 7E9H 7EAH 7FFH 7E9H 7EAH 7FFH
Test program areaNote
Test program areaNote
Note The unmounted area and test program area are so designed that a program or data placed in either of them by mistake is returned to the 000H address.
2.5 Data Memory (RAM): 32 x 4 Bits
The data memory, which is a static RAM consisting of 32 x 4 bits, is used to retain processed data. The data memory is sometimes processed in 8-bit units. R0 can be used as the ROM data pointer. RF is also used as the ASR. When reset, R0 is cleared to "00H" and R1 to RF retain the previous data (undefined when turning on the power).
10
Data Sheet U14380EJ2V0DS00
PD64A, 65
Figure 2-4. Data Memory Organization
R1n (high-order 4 bits) R0n (low-order 4 bits) DP (refer to 2.6 Data Pointer (DP)) R0 R10 R00 R1 R11 R01 R2 R12 R02 R3 R13 R03 R4 R14 R04 R5 R15 R05 R6 R16 R06 R7 R17 R07 R8 R18 R08 R9 R19 R09 RA R1A R0A RB R1B R0B RC R1C R0C RD R1D R0D RE R1E R0E RF R1F R0F ASR (refer to 2.3 Address Stack Register (ASR (RF)))
2.6 Data Pointer (DP): 11 Bits
The ROM data table can be referenced by setting the ROM address in the data pointer to call the ROM contents. The low-order 8 bits of the ROM address are specified by R0 of the data memory; and the high-order 3 bits by bits 4, 5, and 6 of the P3 register (CR0). When reset, the pointer contents become "000H". Figure 2-5. Data Pointer Organization
P3 Register b6 P3 DP10
Note
b5 DP9
b4 DP8 DP7 DP6
R10 DP5 DP4 DP3 DP2
R00 DP1 DP0 R0
Note Set DP10 of the PD64A to "0".
2.7 Accumulator (A): 4 Bits
The accumulator, which refers to a register consisting of 4 bits, plays a leading role in performing various operations. When reset, the accumulator contents are left undefined. Figure 2-6. Accumulator Organization
A3
A2
A1
A0
A
Data Sheet U14380EJ2V0DS00
11
PD64A, 65
2.8 Arithmetic and Logic Unit (ALU): 4 Bits
The arithmetic and logic unit (ALU), which refers to an arithmetic circuit consisting of 4 bits, executes simple manipulations with priority given to logical operations.
2.9 Flags
2.9.1 Status flag (F) Pin and timer statuses can be checked by executing the STTS instruction to check the status flag. The status flag is set (to 1) in the following cases. * If the condition specified with the operand is met when the STTS instruction has been executed * When STANDBY mode is released. * When the release condition is met at the point of executing the HALT instruction. (In this case, the system is not placed in STANDBY mode.) Conversely, the status flag is cleared (to 0) in the following cases: * If the condition specified with the operand is not met when the STTS instruction has been executed. * When the status flag has been set (to 1), the HALT instruction executed, but the release condition is not met at the point of executing the HALT instruction. (In this case, the system is not placed in STANDBY mode.) Table 2-1. Conditions for Status Flag (F) To Be Set by STTS Instruction
Operand Value of STTS Instruction b3 0 b2 0 0 1 1 1 b1 0 1 1 0 b0 0 1 0 1 High level is input to at least one of KI pins. High level is input to at least one of KI pins. High level is input to at least one of KI pins. The down counter of the timer is 0. [The following condition is added in addition to the above.] High level is input to at least one of S0, S1, and S2Note pins.
Condition for Status Flag (F) To Be Set
Either of the combinations of b2, b1, and b0 above.
Note The use of STOP mode release for the S2 pin must be enabled (bit 3 of P4 register is set to 1.)
12
Data Sheet U14380EJ2V0DS00
PD64A, 65
2.9.2 Carry flag (CY) The carry flag is set (to 1) in the following cases: * If the ANL instruction or the XRL instruction is executed when bit 3 of the accumulator is "1" and bit 3 of the operand is "1". * If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is "1". * If the INC instruction or the SCAF instruction is executed when the value of the accumulator is 0FH. The carry flag is cleared (to 0) in the following cases: * If the ANL instruction or the XRL instruction is executed when at least either bit 3 of the accumulator or bit 3 of the operand is "0". * If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is "0". * If the INC instruction or the SCAF instruction is executed when the value of the accumulator is other than 0FH. * If the ORL instruction is executed. * When Data is written to the accumulator by the MOV instruction or the IN instruction.
Data Sheet U14380EJ2V0DS00
13
PD64A, 65
3. PORT REGISTERS (PX)
The KI/O port, the KI port, the special ports (S0, S1/LED, S2), and the control register are treated as port registers. At reset, port register values are shown below. Figure 3-1. Port Register Organization
Port Register P0 P10 KI/O7 KI/O6 KI/O5 KI/O4 P1 P11 KI3 KI2 KI1 KI0 S1/LED S0 P01 S2 1 03H P03 DP9 DP8 TCTL CARY MOD1 MOD0 26H P04 S0 mode KI/O3 KI/O2 P00 KI/O1 KI/O0 FFH
At Reset
xFHNote
P3 (Control register 0) P13 0 DP10
P4 (Control register 1) P14 0 0
KI S0/S1 S2 S1/LED mode KI/O mode pull-down pull-down STOP release
Note
x: Refers to the value based on the KI pin state. Table 3-1. Relationship between Ports and their Read/Write
INPUT Mode Read KI/O KI S0 S1/LED S2 Pin state Pin state Pin state Pin state Pin state Write Output latch -- -- -- -- Note Pin state -- OUTPUT Mode Read Output latch -- Write Output latch -- -- -- --
Port Name
Note When in OFF mode, "1" is normally read.
14
Data Sheet U14380EJ2V0DS00
PD64A, 65
3.1 KI/O Port (P0)
The KI/O port is an 8-bit input/output port for key scan output. INPUT/OUTPUT mode is set by bit 1 of the P4 register. If a read instruction is executed, the pin state can be read in INPUT mode, whereas the output latch contents can be read in OUTPUT mode. If the write instruction is executed, data can be written to the output latch regardless of INPUT or OUTPUT mode. When reset, the port is placed in OUTPUT mode; and the value of the output latch (P0) becomes 1111 1111B. The KI/O port contains the pull-down resistor, allowing pull-down in INPUT mode only. Caution During double pressing of a key, a high-level output and a low-level output may coincide with each other at the KI/O port. To avoid this, the low-level output current of the KI/O port is held low. Therefore, be careful when using the KI/O port for purposes other than key scan output. The KI/O port is so designed that, even when connected directly to VDD within the normal supply voltage range (VDD = 2.0 to 3.6 V), no problem may occur. Table 3-2. KI/O Port (P0)
Bit Name b7 KI/O7 b6 KI/O6 b5 KI/O5 b4 KI/O4 b3 KI/O3 b2 KI/O2 b1 KI/O1 b0 KI/O0
b0-b7
: In reading : In INPUT mode, the KI/O pin's state is read. In OUTPUT mode, the KI/O pin's output latch contents are read. In writing : Data is written to the KI/O pin's output latch regardless of INPUT or OUTPUT mode.
Data Sheet U14380EJ2V0DS00
15
PD64A, 65
3.2 KI Port/Special Ports (P1)
3.2.1 KI port (P11: bits 4-7 of P1) The KI port is to the 4-bit input port for key entry. The pin state can be read. Software can be used to set the availability of the pull-down resistor of the KI port in 4-bit units by means of bit 5 of the P4 register. When reset, the pull-down resistor is connected. Table 3-3. KI/Special Port Register (P1)
Bit Name b7 KI3 b6 KI2 b5 KI1 b4 KI0 b3 S1/LED b2 S0 b1 S2 b0
Fixed to "1"
b1 b2 b3 b4-b7
: The state of the S2 pin is read (Read only). : In INPUT mode, state of the S0 pin is read (Read only). In OFF mode, this bit is fixed to "1". : The state of the S1/LED pin is read regardless of INPUT/OUTPUT mode (Read only). : The state of the KI pin is read (Read only).
Caution In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when POC is released due to supply voltage startup. 3.2.2 S0 port (bit 2 of P1) The S0 port is an INPUT/OFF mode port. The pin state can be read by setting this port to INPUT mode with bit 0 of the P4 register. In INPUT mode, software can be used to set the availability of the pull-down resistor of the S0 and S1/LED port in 2-bit units by means of bit 4 of the P4 register. If INPUT mode is released (thus set to OFF mode), the pin becomes high-impedance but it also makes that the through current does not flow internally. In OFF mode, "1" can be read regardless of the pin state. When reset, it is set to OFF mode, thus becoming high-impedance. 3.2.3 S1/LED (bit 3 of P1) The S1/LED port is an input/output port. It uses bit 2 of the P4 register to set INPUT or OUTPUT mode. The pin state can be read in both INPUT mode and OUTPUT mode. When in INPUT mode, software can be used to set the availability of the pull-down resistor of the S0 and S1/LED ports in 2-bit units by means of bit 4 of the P4 register. When in OUTPUT mode, the pull-down resistor is automatically disconnected thus becoming the remote control transmission display pin (refer to 4. TIMER). When reset, it is placed in OUTPUT mode, and high level is output.
16
Data Sheet U14380EJ2V0DS00
PD64A, 65
3.2.4 S2 port (bit 1 of P1) The S2 port is an input port. Use of the STOP mode release of the S2 port can be specified by bit 3 of the P4 register. When using the pin as a key input from a key matrix, enable (bit 3 of P4 register is set to 1) the use of the STOP mode release (at this time, a pull-down resistor is connected internally.) When the STOP mode release is disabled (bit 3 of P4 register is set to 0), it can be used as the input port which does not release the STOP mode even if the release condition is established (at this time, a pull-down resistor is not connected internally.) The state of the pin can be read in both cases. At reset, the pin is set to INPUT mode where the STOP mode release is disabled, and goes to high-impedance state.
3.3 Control Register 0 (P3)
Control register 0 consists of 8 bits. The contents that can be controlled are as shown below. When reset, the register becomes 0000 0011B. Table 3-4. Control Register 0 (P3)
Bit Name b7 -- b6 DP10Note Set value 0 1 Fixed to "0" 0 0 1 0 b5 b4 b3 TCTL b2 CARY b1 MOD1 b0 MOD0
DP (Data pointer) DP9 0 1 0 DP8 0 1 0
1/1 1/2 0
ON OFF 0
Refer to Table 3-5.
When reset 0
1
1
b0, b1 : These bits specify the carrier frequency and duty ratio of the REM output. b2 b3 : This bit specifies the availability of the carrier of the frequency specified by b0 and b1. "0" = ON (with carrier); "1" = OFF (without carrier; high level) : This bit changes the carrier frequency and the timer clock's frequency division ratio. "0" = 1/1 (carrier frequency: the specified value of b0 and b1; timer clock: fX/64) "1" = 1/2 (carrier frequency: half of the specified value of b0 and b1; timer clock: fX/128) Table 3-5. Timer Clock and Carrier Frequency Setup
b3 0 0 b2 0 0 1 1 1 0 0 x 0 0 1 1 1 x b1 0 1 0 1 x 0 1 0 1 x fX/128 b0 Timer Clock fX/64 Carrier Frequency (Duty Ratio) fX/8 (Duty 1/2) fX/64 (Duty 1/2) fX/96 (Duty 1/2) fX/96 (Duty 1/3) Without carrier (high level) fX/16 (Duty 1/2) fX/128 (Duty 1/2) fX/192 (Duty 1/2) fX/192 (Duty 1/3) Without carrier (high level)
b4, b5, b6 : These bits specify the high-order 3 bits (DP8, DP9 and DP10) of ROM's data pointer. Note Set DP10 of the PD64A to "0". Remark x: don't care
Data Sheet U14380EJ2V0DS00
17
PD64A, 65
3.4 Control Register 1 (P4)
Control register 1 consists of 8 bits. The contents that can be controlled are as shown below. When reset, the register becomes 0010 0110B. Table 3-6. Control Register 1 (P4)
Bit Name b7 -- b6 -- b5 KI b4 S0/S1 b3 S2 b2 S1/LED b1 KI/O mode IN OUT 1 b0 S0 mode OFF IN 0
Pull-down Pull-down STOP release mode Set value 0 1 Fixed to "0" 0 Fixed to "0" 0 OFF ON 1 OFF ON 0 Disable Enable 0 S1 LED 1
When reset
b0 : Specifies the input mode of the S0 port. "0" = OFF mode (high impedance); "1" = IN (INPUT mode). b1 : Specifies the I/O mode of the KI/O port. "0" = IN (INPUT mode); "1" = OUT (OUTPUT mode). b2 : Specifies the I/O mode of the S1/LED port. "0" = S1 (INPUT mode); "1" = LED (output mode). b3 : Specified the use of the STOP mode release by S2 port (with/without pull-down resistor). "0" = disable (pulldown unavailable); "1" = enable (pull-down available). b4 : Specifies the availability of the pull-down resistor in S0/S1 port INPUT mode. "0" = OFF (unavailable); "1" = ON (available) b5 : Specifies the availability of the pull-down resistor in KI port. "0" = OFF (unavailable); "1" = ON (available). Remark In OUTPUT mode or in OFF mode, all the pull-down resistors are automatically disconnected.
18
Data Sheet U14380EJ2V0DS00
PD64A, 65
4. TIMER 4.1 Timer Configuration
The timer is the block used for creating a remote control transmission pattern. As shown in Figure 4-1, it consists of a 9-bit down counter (t8 to t0), a flag (t9) permitting the 1-bit timer output, and a zero detecting circuit. Figure 4-1. Timer Configuration
T T1 t9 t8 t7 t6 T0 t5 t4 t3 t2 9-bit down counter t1 t0
Bit 3 of control register 0 (P3)
Selector
Count clock
fX/64 fX/128
S1/LED
Carrier synchronous circuit
Timer operation end signal (HALT # x101B release signal) Zero detecting circuit
REM
Bit 2 of control register 0 (P3) Carrier signal
Data Sheet U14380EJ2V0DS00
19
PD64A, 65
4.2 Timer Operation
The timer starts (counting down) when a value other than 0 is set for the down counter with a timer operation instruction. The timer operation instructions for making the timer start operation are shown below: MOV T0, A MOV T1, A MOV T, #data10 MOV T, @R0 The down counter is decremented (-1) in the cycle of 64/fX or 128/fXNote. If the value of the down counter becomes 0, the zero detecting circuit generates the timer operation end signal to stop the timer operation. At this time, if the timer is in HALT mode (HALT #x101B) waiting for the timer to stop its operation, the HALT mode is released and the instruction following the HALT instruction is executed. The output of the timer operation end signal is continued while the down counter is 0 and the timer is stopped. There is the following relational expression between the timer's time and the down counter's set value. Timer time = (Set value + 1) x 64/fX (or 128/fXNote) Note This becomes 128/fX if bit 3 of the control register is set (to 1). By setting 1 for the flag (t9) which enables the timer output, the timer can output its operation status from the S1/LED pin and the REM pin. The REM pin can also output the carrier while the timer is in operation. Table 4-1. Timer Output (at t9 = 1)
S1/LED Pin Timer operating Timer halting L H REM Pin H (or carrier output Note) L
Note The carrier output results if bit 2 of the control register 0 is cleared (to 0). Figure 4-2. Timer Output (when carrier is not output)
Timer value: (set value + 1) x 64/fX (or 128/fX)
LED
REM
20
Data Sheet U14380EJ2V0DS00
PD64A, 65
4.3 Carrier Output
The carrier for remote-controlled transmission can be output from the REM pin by clearing (to 0) bit 2 of the control register 0. As shown in Figure 4-3, in the case where the timer stops when the carrier is at a high level, the carrier continues to be output until its next fall and then stops due to the function of the carrier synchronous circuit. When the timer starts operation, however, the high-level width of the first carrier may become shorter than the specified width. Figure 4-3. Timer Output (when carrier is output)
Timer value: (Set value+1) x 64/fX (or 128/fX)
LED
REM (at low-level start) Note 1 REM (at high-level start)
Note 2
Notes 1. Error when the REM output ends: Lead by "the carrier's low-level width" to lag by "the carrier's highlevel width" 2. Error of the carrier's high-level width: 0 to "the carrier's high-level width"
4.4 Software Control of Timer Output
The timer output can be controlled by software. As shown in Figure 4-4, the pulse with a minimum width of 1instruction cycle (64/fX) can be output. Figure 4-4. Pulse Output of 1-Instruction Cycle Width MOV T, #0000000000B; low-level output from the REM pin MOV T, #1000000000B; high-level output from the REM pin MOV T, #0000000000B; low-level output from the REM pin ... ... ...
64/fX
LED
REM
Data Sheet U14380EJ2V0DS00
21
PD64A, 65
5. STANDBY FUNCTION 5.1 Outline of Standby Function
To save current consumption, two types of standby modes, i.e., HALT mode and STOP mode, are made available. In STOP mode, the system clock stops oscillation. At this time, the XIN and XOUT pins are fixed at a low level. In HALT mode, CPU operation halts, while the system clock continues oscillation. When in HALT mode, the timer (including REM output and LED output) operates. In either STOP mode or HALT mode, the statuses of the data memory, accumulator, and port register, etc. immediately before the standby mode is set are retained. Therefore, make sure to set the port status for the system so that the current consumption of the whole system is suppressed before the standby mode is set. Table 5-1. Statuses during Standby Mode
STOP Mode Setting instruction Clock oscillation circuit CPU Data memory Operation statuses Accumulator Flag F CY Port register Timer HALT instruction Oscillation stopped * Operation halted * Immediately preceding status retained * Immediately preceding status retained * 0 (When 1, the flag is not placed in the standby mode.) * Immediately preceding status retained * Immediately preceding status retained * Operation halted * Operable (The count value is reset to "0") Oscillation continued HALT Mode
Cautions 1. Write the NOP instruction as the first instruction after STOP mode is released. 2. When standby mode is released, the status flag (F) is set (to 1). 3. If, at the point the standby mode has been set, its release condition is met, then the system is not placed in the standby mode. However, the status flag (F) is set (1).
22
Data Sheet U14380EJ2V0DS00
PD64A, 65
5.2 Standby Mode Setup and Release
The standby mode is set with the HALT #b3b2b1b0B instruction for both STOP mode and HALT mode. For the standby mode to be set, the status flag (F) is required to have been cleared (to 0). The standby mode is released by the release condition specified with the reset (POC) or the operand of HALT instruction. If the standby mode is released, the status flag (F) is set (to 1). Even when the HALT instruction is executed in the state that the status flag (F) has been set (to 1), the standby mode is not set. If the release condition is not met at this time, the status flag is cleared (to 0). If the release condition is met, the status flag remains set (to 1). Even in the case when the release condition has been already met at the point that the HALT instruction is executed, the standby mode is not set. Here, also, the status flag (F) is set (to 1). Caution Depending on the status of the status flag (F), the HALT instruction may not be executed. Be careful about this. For example, when setting HALT mode after checking the key status with the STTS instruction, the system does not enter HALT mode as long as the status flag (F) remains set (to 1) thus sometimes performing an unintended operation. In this case, the intended operation can be realized by executing the STTS instruction immediately after timer setting to clear (to 0) the status flag. Example STTS MOV STTS HALT ... ... #03H T, #0xxH #05H #05H ;To check the KI pin status. ;To set the timer ;To clear the status flag ;To set HALT mode
(During this time, be sure not to execute an instruction that may set the status flag.)
Table 5-2. Addresses Executed after Standby Mode Release
Release Condition Reset Release condition shown in Table 5-3 Address Executed after Release 0 address The address following the HALT instruction
Data Sheet U14380EJ2V0DS00
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PD64A, 65
Table 5-3. Standby Mode Setup (HALT #b3b2b1b0B) and Release Conditions
Operand Value of HALT Instruction b3 0 b2 0 0 1 1 b1 0 1 1 b0 0 1 0 STOP STOP STOPNote 1 STOP All KI/O pins are high-level output. All KI/O pins are high-level output. The KI/O0 pin is high-level output. High level is input to at least one of KI pins. High level is input to at least one of KI pins. High level is input to at least one of KI pins.
Setting Mode
Precondition for Setup
Release Condition
Any of the combinations of b2b1b0 above
[The following condition is added in addition to the above.] -- High level is input to at least one of S0, S1 and S2 pins Note 2.
0/1
1
0
1
HALT
--
When the timer's down counter is 0
Notes 1. When setting HALT #x110B, configure a key matrix by using the KI/O0 pin and the KI pin so that an internal reset takes effect at the time of program hang-up. 2. At least one of the S0, S1 and S2 pins (the pin used for releasing the standby) must be specified as follows: S0, S1 pins : INPUT mode (specified by bits 0 and 2 of the P4 register) S2 pin : Use of STOP mode release enabled (specified by bit 3 of the P4 register)
Cautions 1. The internal reset takes effect when the HALT instruction is executed with an operand value other than that above or when the precondition has not been satisfied when executing the HALT instruction. 2. If STOP mode is set when the timer's down counter is not 0 (timer operating), the system is placed in STOP mode only after all the 10 bits of the timer's down counter and the timer output permit flag are cleared to 0. 3. Write the NOP instruction as the first instruction after STOP mode is released.
24
Data Sheet U14380EJ2V0DS00
PD64A, 65
5.3 Standby Mode Release Timing
(1) STOP Mode Release Timing Figure 5-1. STOP Mode Release by Release Condition
Wait (52/fX + )
HALT instruction (STOP mode) Standby release signal OPERATING mode STOP mode Oscillation stopped
HALT mode
OPERATING mode
Oscillation Clock
Oscillation : Oscillation growth time
Caution When a release condition is established in the STOP mode, the device is released from the STOP mode, and goes into a wait state. At this time, if the release condition is not held, the device goes into STOP mode again after the wait time has elapsed. Therefore, when releasing the STOP mode, it is necessary to hold the release condition longer than the wait time. (2) HALT Mode Release Timing Figure 5-2. HALT Mode Release by Release Condition
Standby release signal
HALT instruction (HALT mode) OPERATING mode
HALT mode
OPERATING mode
Oscillation Clock
Data Sheet U14380EJ2V0DS00
25
PD64A, 65
6. RESET
The system reset takes effect by means of the causes as follows: * When the POC circuit has detected low-power voltage * When the operand value is illegal or does not satisfy the precondition when the HALT instruction is executed * When the accumulator is 0H when the RLZ instruction is executed * When stack pointer overflows or underflows Table 6-1. Hardware Statuses after Reset
* Resetting by Internal POC Circuit in Operation * Resetting by Other FactorsNote 1 000H 0B R0 = DP R1-RF 000H Undefined Undefined 0B 0B 000H P0 P1 Control register P3 P4 FFH xxxx 11x1BNote 2 03H 26H Previous status retained * Resetting by the Internal POC Circuit during STANDBY Mode
Hardware PC (11 bits) SP (1 bit) Data memory
Accumulator (A) Status flag (F) Carry flag (CY) Timer (10 bits) Port register
Notes 1. The following resets are available. * Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy the precondition) * Reset when executing the RLZ instruction (when A = 0) * Reset by stack pointer's overflow or underflow 2. Refers to the value by the KI or S2 pin status. In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when POC is released due to supply voltage startup.
26
Data Sheet U14380EJ2V0DS00
PD64A, 65
7. POC CIRCUIT
The POC circuit monitors the power supply voltage and applies an internal reset in the microcontroller at the time of battery replacement. Cautions 1. There are cases in which the POC circuit cannot detect a low power supply voltage of less than 1 ms. Therefore, if the power supply voltage has become low for a period of less than 1 ms, the POC circuit may malfunction because it does not generate an internal reset signal. 2. Clock oscillation is stopped by the resonator due to low power supply voltage before the POC circuit generates the internal reset signal. In this case, malfunction may result, for example when the power supply voltage is recovered after the oscillation is stopped. This type of phenomenon takes place because the POC circuit does not generate an internal reset signal (because the power supply voltage recovers before the low power supply voltage is detected) even though the clock has stopped. If, by any chance, a malfunction has taken place, remove the battery for a short time and put it back. In most cases, normal operation will be resumed. 3. In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when POC is released due to supply voltage startup).
Data Sheet U14380EJ2V0DS00
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PD64A, 65
7.1 Functions of POC Circuit
The POC circuit has the following functions: * Generates an internal reset signal when VDD VPOC. * Cancels an internal reset signal when VDD > VPOC. Here, VDD: power supply voltage, VPOC: POC-detected voltage.
VDD 3.6 V Clock frequency fX = 2.4 to 8 MHz 2.0 V VPOC Approx. 1.7 V POC-detected voltage VPOC = 1.85 V (TYP.)Note 3 Operating ambient temperature TA = - 40 to + 85C
0V
t
Internal reset signal Note 1 OPERATING mode Reset Note 2
Reset
Notes 1. In reality, there is the oscillation stabilization wait time until the circuit is switched to OPERATING mode. The oscillation stabilization wait time is about 252/fX to 700/fX (when about 70 to 190 s; fX = 3.64 MHz). 2. For the POC circuit to generate an internal reset signal when the power supply voltage has fallen, it is necessary for the power supply voltage to be kept less than the VPOC for the period of 1 ms or more. Therefore, in reality, there is the time lag of up to 1 ms until the reset takes effect. 3. The POC-detected voltage (VPOC) varies between approximately 1.7 to 2.0 V; thus, the resetting may be canceled at a power supply voltage smaller than the assured range (VDD = 2.0 to 3.6 V). However, as long as the conditions for operating the POC circuit are met, the actual lowest operating power supply voltage becomes lower than the POC-detected voltage. Therefore, there is no malfunction occurring due to the shortage of power supply voltage. However, malfunction for such reasons as the clock not oscillating due to low power supply voltage may occur (refer to Cautions 3. in 7. POC CIRCUIT).
7.2 Oscillation Check at Low Supply Voltage
A reliable resetting operation can be expected of the POC circuit if it satisfies the condition that the clock can oscillate even at low power supply voltage (the oscillation start voltage of the resonator being even lower than the POC-detected voltage). Whether this condition is being met or not can be checked by measuring the oscillation status on a product which actually contains a POC circuit, as follows. <1> Connect a storage oscilloscope to the XOUT pin so that the oscillation status can be measured. <2> Connect a power supply whose output voltage can be varied and then gradually raise the power supply voltage VDD from 0 V (making sure to avoid VDD > 3.6V). At first (during VDD < approx. 1.7 V), the XOUT pin is 0 V regardless of the VDD. However, at the point that VDD reaches the POC-detected voltage (VPOC = 1.85 V (TYP.)), the voltage of the XOUT pin jumps to about 0.5 VDD. Maintain this power supply voltage for a while to measure the waveform of the XOUT pin. If, by any chance, the oscillation start voltage of the resonator is lower than the POC-detected voltage, the growing oscillation of the XOUT pin can be confirmed within several ms after the VDD has reached the VPOC.
28
Data Sheet U14380EJ2V0DS00
PD64A, 65
8. SYSTEM CLOCK OSCILLATOR
The system clock oscillator consists of oscillators for ceramic resonators (fX = 2.4 to 8 MHz). Figure 8-1. System Clock
PD64A, 65
XOUT
XIN
GND
Ceramic resonator
The system clock oscillator stops its oscillation when reset or in STOP mode. Caution When using the system clock oscillator, wire area indicated by the dotted-line in the diagram as follows to reduce the effects of the wiring capacitance, etc. * Make the wiring as short as possible. * Do not allow the wiring to intersect other signal lines. Do not wire close to lines through which large fluctuating currents flow. * Make sure that the point where the oscillator capacitor is installed is always at the same electric potential as the ground. Never earth with a ground pattern through which large currents flow. * Do not extract signals from the oscillator.
Data Sheet U14380EJ2V0DS00
29
PD64A, 65
9. INSTRUCTION SET 9.1 Machine Language Output by Assembler
The bit length of the machine language of this product is 10 bits per word. However, the machine language that is output by the assembler is extended to 16 bits per word. As shown in the example below, the expansion is made by inserting 3-bit extended bits (111) in two locations. Figure 9-1. Example of Assembler Output (10 bits extended to 16 bits) <1> In the case of "ANL A, @R0H"
1
1010
1
0000
111
1
1010
111
1
0000
= FAF0
Extended bits
Extended bits
<2> In the case of "OUT P0, #data8"
0
0110
1
1000
111
0
0110
111
1
1000
= E6F8
Extended bits
Extended bits
30
Data Sheet U14380EJ2V0DS00
PD64A, 65
9.2 Circuit Symbol Description
A ASR addr CY data4 data8 data10 F PC Pn P0n P1n ROMn Rn R0n R1n SP T T0 T1 (x) : Accumulator : Address Stack Register : Program memory address : Carry flag : 4-bit immediate data : 8-bit immediate data : 10-bit immediate data : Status flag : Program Counter : Port register pair (n = 0, 1, 3, 4) : Port register (low-order 4 bits) : Port register (high-order 4 bits) : Bit n of the program memory's (n = 0-9) : Register pair : Data memory (General-purpose register; n = 0-F) : Data memory (General-purpose register; n = 0-F) : Stack Pointer : Timer register : Timer register (low-order 4 bits) : Timer register (high-order 4 bits) : Content addressed with x
Data Sheet U14380EJ2V0DS00
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PD64A, 65
9.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table
Accumulator Operation Instructions
Instruction Code 1st Word ANL A, R0n A, R1n A, @R0H FBEn FAEn FAF0 2nd Word 3rd Word CY A3 * Rmn3 CY A3 * ROM7 A, @R0L FBF0 CY A3 * ROM3 A, #data4 FBF1 data4 CY A3 * data43 ORL A, R0n A, R1n A, @R0H FDEn FCEn FCF0 (A) (A) (Rmn) CY 0 (A) (A) ((P13), (R0))7-4 CY 0 A, @R0L FDF0 (A) (A) ((P13), (R0))3-0 CY 0 A, #data4 FDF1 data4 (A) (A) data4 CY 0 XRL A, R0n A, R1n A, @R0H F5En F4En F4F0 (A) (A) (Rmn) CY A3 * Rmn3 (A) (A) ((P13), (R0))7-4 CY A3 * ROM7 A, @R0L F5F0 (A) (A) ((P13), (R0))3-0 CY A3 * ROM3 A, #data4 F5F1 data4 (A) (A) data4 CY A3 * data43 INC A F4F3 (A) (A) + 1 if (A) = 0 CY 1 else CY 1 RL A FCF3 (An+1) (An), (A0) (A3) CY A3 RLZ A FEF3 if A = 0 CY A3 reset else (An+1) (An), (A0) (A3) 1 2 m = 0, 1 n = 0-F 1 2 m = 0, 1 n = 0-F 1

Mnemonic
Operand
Operation (A) (A) (A) (A) (A) (A) (A) (A) (Rmn) m = 0, 1 n = 0-F
Instruction Length 1
Instruction Cycle 1
32
Data Sheet U14380EJ2V0DS00
((P13), (R0))7-4
((P13), (R0))3-0
data4
2
PD64A, 65
Input/output Instructions
Instruction Code 1st Word IN A, P0n A, P1n OUT P0n, A P1n, A ANL A, P0n A, P1n ORL A, P0n A, P1n XRL A, P0n A, P1n FFF8 + n FEF8 + n E5F8 + n E4F8 + n FBF8 + n FAF8 + n FDF8 + n FCF8 + n F5F8 + n F4F8 + n 2nd Word -- -- -- -- -- -- -- -- -- -- 3rd Word -- -- -- -- -- -- -- -- -- -- CY A3 * Pmn3 (A) (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4 CY 0 (A) (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4 CY A3 * Pmn3 Instruction Length (Pn) data8 n = 0, 1, 3, 4 2 1 Instruction Cycle (A) (Pmn) CY 0 (Pmn) (A) m = 0, 1 n = 0, 1, 3, 4 m = 0, 1 n = 0, 1, 3, 4 1 Instruction Length 1 Instruction Cycle
Mnemonic
Operand
Operation
Mnemonic OUT
Operand
Instruction Code 1st Word 2nd Word data8 3rd Word
Pn, #data8 E6F8 + n
Remark
Pn: P1n-P0n are dealt with in pairs.
Data Transfer Instruction
Instruction Code 1st Word MOV A, R0n A, R1n A, @R0H FFEn FEEn FEF0 2nd Word 3rd Word (A) (Rmn) CY 0 (A) ((P13), (R0))7-4 CY 0 A, @R0L FFF0 (A) ((P13), (R0))7-4 CY 0 A, #data4 R0n, A R1n, A FFF1 E5En E4En data4 (A) data4 CY 0 (Rmn) (A) m = 0, 1 n = 0-F 2 1 m = 0, 1 n = 0-F 1 Instruction Length 1 Instruction Cycle
Mnemonic
Operand
Mnemonic MOV
Operand Rn, #data8 E6En Rn, @R0 E7En
Instruction Code 1st Word 2nd Word data8 -- 3rd Word -- --
(R1n-R0n) data8 (R1n-R0n) ((P13), (R0))
Remark
Rn: R1n-R0n are dealt with in pairs.
Data Sheet U14380EJ2V0DS00
(A) (A)
(Pmn) m = 0, 1 n = 0, 1, 3, 4
Operation
Operation
Operation n = 0-F n = 1-F
Instruction Length 2 1
Instruction Cycle 1
33
PD64A, 65
Branch Instructions
Instruction Code 1st Word JMP addr (Page 0) E8F1 addr (Page 1) E9F1 JC addr (Page 0) ECF1 addr (Page 1) EAF1 JNC addr (Page 0) EDF1 addr (Page 1) EBF1 JF addr (Page 0) EEF1 addr (Page 1) F0F1 JNF addr (Page 0) EFF1 addr (Page 1) F1F1 2nd Word addr addr addr addr addr addr addr addr addr addr if CY = 1 PC addr PC addr PC addr PC addr else PC PC + 2 if CY = 0 else PC PC + 2 if F = 1 else PC PC + 2 if F = 0 else PC PC + 2 3rd Word PC addr 2 Instruction Length 1 Instruction Cycle
Mnemonic
Operand
Operation
Caution 0 and 1, which refer to PAGE0 and 1, are not written when describing mnemonics. Subroutine Instructions
Instruction Code 1st Word CALL addr (Page 0) E6F2 addr (Page 1) E6F2 RET E8F2 2nd Word E8F1 E9F1 3rd Word addr addr PC ASR, SP SP - 1 1 1 SP SP + 1, ASR PC, PC addr 3 Instruction Length 2 Instruction Cycle
Mnemonic
Operand
Operation
Caution 0 and 1, which refer to PAGE0 and 1, are not written when describing mnemonics. Timer Operation Instructions
Instruction Code 1st Word MOV A, T0 A, T1 T0, A T1, A FFFF FEFF E5FF F4FF 2nd Word 3rd Word (A) (Tn) CY 0 (Tn) (A) (T) n 0 Instruction Code 1st Word MOV T, #data10 T, @R0 E6FF F4FF 2nd Word data10 3rd Word (T) data10 (T) ((P13), (R0)) 1 Instruction Length 1 Instruction Cycle n = 0, 1 n = 0, 1 1 Instruction Length 1 Instruction Cycle
Mnemonic
Operand
Operation
Mnemonic
Operand
Operation
34
Data Sheet U14380EJ2V0DS00
PD64A, 65
Others
Instruction Code 1st Word HALT STTS #data4 #data4 E2F1 E3F1 2nd Word data4 data4 3rd Word Standby mode if statuses match else R0n E3En F0 F1 n = 0-F CY 1 1 F0 CY 0 F1 2 Instruction Length 1 Instruction Cycle
Mnemonic
Operand
Operation
if statuses match else
SCAF
FAF3
if A = 0FH else
NOP
E0E0
PC PC + 1
Data Sheet U14380EJ2V0DS00
35
PD64A, 65
9.4 Accumulator Operation Instructions
ANL A, R0n ANL A, R1n <1> Instruction code : <2> Cycle count <3> Function
1 1 0 1 R4 0 R3 R2 R1 R0
:1 CY A3 * Rmn3

: (A) (A)
(Rmn)
m = 0, 1
n = 0 to F
The accumulator contents and the register Rmn contents are ANDed and the results are entered in the accumulator. ANL A, @R0H ANL A, @R0L <1> Instruction code : <2> Cycle count <3> Function
1 1 0 1 0/1 1 0 0 0 0
:1 : (A) (A) (A) (A) ((P13), (R0))7-4 (in the case of ANL A, @R0H) ((P13), (R0))3-0 (in the case of ANL A, @R0L) CY A3 * ROM7 CY A3 * ROM3
The accumulator contents and the program memory contents specified with the control register P13 and register pair R10-R00 are ANDed and the results are entered in the accumulator. If H is specified, b7, b6, b5 and b4 take effect. If L is specified, b3, b2, b1 and b0 take effect. * Program memory (ROM) organization
b9
b7
b6
b5
b4
b8
b3
b2
b1
b0
H
L
Valid bits at the time of accumulator operation
ANL A, #data4 <1> Instruction code : <2> Cycle count <3> Function
1 101110001 0 0 0 0 0 0 d3 d2 d1 d0
:1 CY A3 * data43
: (A) (A)
data4
The accumulator contents and the immediate data are ANDed and the results are entered in the accumulator.
36
Data Sheet U14380EJ2V0DS00
PD64A, 65
ORL A, R0n ORL A, R1n <1> Instruction code : <2> Cycle count <3> Function
1 1 1 0 R4 0 R3 R2 R1 R0
:1 : (A) (A) (Rmn) CY 0 m = 0, 1 n = 0 to F
The accumulator contents and the register Rmn contents are ORed and the results are entered in the accumulator. ORL A, @R0H ORL A, @R0L <1> Instruction code : <2> Cycle count <3> Function
1 1 1 0 0/1 1 0 0 0 0
:1 : (A) (A) (P13), (R0))7-4 (in the case of ORL A, @R0H) (A) (A) (P13), (R0))3-0 (in the case of ORL A, @R0L) CY 0
The accumulator contents and the program memory contents specified with the control register P13 and register pair R10-R00 are ORed and the results are entered in the accumulator. If H is specified, b7, b6, b5 and b4 take effect. If L is specified, b3, b2, b1 and b0 take effect. ORL A, #data4 <1> Instruction code : <2> Cycle count <3> Function
1 110110001 0 0 0 0 0 0 d3 d2 d1 d0
:1 : (A) (A) data4 CY 0
The accumulator contents and the immediate data are exclusive-ORed and the results are entered in the accumulator. XRL A, R0n XRL A, R1n <1> Instruction code : <2> Cycle count <3> Function
1 0 1 0 R4 0 R3 R2 R1 R0
:1 : (A) (A) (Rmn) CY A3 * Rmn3 m = 0, 1 n = 0 to F
The accumulator contents and the register Rmn contents are ORed and the results are entered in the accumulator.
Data Sheet U14380EJ2V0DS00
37
PD64A, 65
XRL A, @R0H XRL A, @R0L <1> Instruction code : <2> Cycle count <3> Function
1 0 1 0 0/1 1 0 0 0 0
:1 : (A) (A) (P13), (R0))7-4 (in the case of XRL A, @R0H) CY A3 * ROM7 (A) (A) (P13), (R0))3-0 (in the case of XRL A, @R0L) CY A3 * ROM3
The accumulator contents and the program memory contents specified with the control register P13 and register pair R10-R00 are exclusive-ORed and the results are entered in the accumulator. If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b0 take effect. XRL A, #data4 <1> Instruction code : <2> Cycle count <3> Function
1 010110001 0 0 0 0 0 0 d3 d2 d1 d0
:1 : (A) (A) data4 CY A3 * data43
The accumulator contents and the immediate data are exclusive-ORed and the results are entered in the accumulator. INC A <1> Instruction code : <2> Cycle count <3> Function
1 010010011
:1 : (A) (A) + 1 if A=0 CY 1 else CY 0
The accumulator contents are incremented (+1). RL A <1> Instruction code : <2> Cycle count <3> Function
1 110010011
:1 : (An + 1) (An), (A0) (A3) CY A3
The accumulator contents are rotated anticlockwise bit by bit. RLZ A <1> Instruction code : <2> Cycle count <3> Function
1 111010011
:1 : if A=0 reset else (An + 1) (An), (A0) (A3)
CY A3 The accumulator contents are rotated anticlockwise bit by bit. If A = 0H at the time of command execution, an internal reset takes effect.
38
Data Sheet U14380EJ2V0DS00
PD64A, 65
9.5 Input/Output Instructions
IN A, P0n IN A, P1n <1> Instruction code : <2> Cycle count <3> Function
1 1 1 1 P4 1 1 P2 P1 P0
:1 : (A) (Pmn) CY 0 m = 0, 1 n = 0, 1, 3, 4
The port Pmn data is loaded (read) onto the accumulator. OUT P0n, A OUT P1n, A <1> Instruction code : <2> Cycle count <3> Function
0 0 1 0 P4 1 1 P2 P1 P0
:1 : (Pmn) (A) m = 0, 1 n = 0, 1, 3, 4
The accumulator contents are transferred to port Pmn to be latched. ANL A, P0n ANL A, P1n <1> Instruction code : <2> Cycle count <3> Function
1 1 0 1 P4 1 1 P2 P1 P0
:1 CY A3 * Pmn
: (A) (A)
(Pmn)
m = 0, 1
n = 0, 1, 3, 4
The accumulator contents and the port Pmn contents are ANDed and the results are entered in the accumulator. ORL A, P0n ORL A, P1n <1> Instruction code : <2> Cycle count <3> Function
1 1 1 0 P4 1 1 P2 P1 P0
:1 : (A) (A) (Pmn) CY 0 m = 0, 1 n = 0, 1, 3, 4
The accumulator contents and the port Pmn contents are ORed and the results are entered in the accumulator. XRL A, P0n XRL A, P1n <1> Instruction code : <2> Cycle count <3> Function
1 0 1 0 P4 1 1 P2 P1 P0
:1 : (A) (A) (Pmn) CY A3 * Pmn m = 0, 1 n = 0, 1, 3, 4
The accumulator contents and the port Pmn contents are exclusive-ORed and the results are entered in the accumulator.
Data Sheet U14380EJ2V0DS00
39
PD64A, 65
OUT Pn, #data8 <1> Instruction code : : <2> Cycle count <3> Function
0 0 1 1 0 1 1 P2 P1 P0 0 d7 d6 d5 d4 0 d3 d2 d1 d0
:1 : (Pn) data8 n = 0, 1, 3, 4
The immediate data is transferred to port Pn. In this case, port Pn refers to P1n-P0n operating in pairs.
9.6 Data Transfer Instructions
MOV A, R0n MOV A, R1n <1> Instruction code : <2> Cycle count <3> Function
1 1 1 1 R4 0 R3 R2 R1 R0
:1 : (A) (Rmn) CY 0 m = 0, 1 n = 0 to F
The register Rmn contents are transferred to the accumulator. MOV A, @R0H <1> Instruction code : <2> Cycle count <3> Function
1 111010000
:1 : (A) ((P13), (R0))7-4 CY 0
The high-order 4 bits (b7 b6 b5 b4) of the program memory specified with control register P13 and register pair R10-R00 are transferred to the accumulator. b9 is ignored. MOV A, @R0L <1> Instruction code : <2> Cycle count <3> Function
1 111110000
:1 : (A) ((P13), (R0))3-0 CY 0
The low-order 4 bits (b3 b2 b1 b0) of the program memory specified with control register P13 and register pair R10-R00 are transferred to the accumulator. b8 is ignored. * Program memory (ROM) contents
@R0 H b9 b7 b6 b5 b4 b8 b3
@R0 L b2 b1 b0
MOV A, #data4 <1> Instruction code : : <2> Cycle count <3> Function
1 111110001 0 0 0 0 0 0 d3 d2 d1 d0
:1 : (A) data4 CY 0
The immediate data is transferred to the accumulator.
40
Data Sheet U14380EJ2V0DS00
PD64A, 65
MOV R0n, A MOV R1n, A <1> Instruction code : <2> Cycle count <3> Function
0 0 1 0 R4 0 R3 R2 R1 R0
:1 : (Rmn) (A) m = 0, 1 n = 0 to F
The accumulator contents are transferred to register Rmn. MOV Rn, #data8 <1> Instruction code : : <2> Cycle count <3> Function pairs. The pair combinations are as follows: R0 : R10 - R00 R1 : R11 - R01 : RE : R1E - R0E RF : R1F - R0F Lower column Higher column MOV Rn, @R0 <1> Instruction code : <2> Cycle count <3> Function
0 0 1 1 1 0 R3 R2 R1 R0 0 0 1 1 0 0 R3 R2 R1 R0 0 d7 d6 d5 d4 0 d3 d2 d1 d0
:1 : (R1n-R0n) data8 n = 0 to F
The immediate data is transferred to the register. Using this instruction, registers operate as register
:1 : (R1n-R0n) ((P13), R0)) n = 1 to F
The program memory contents specified with control register P13 and register pair R10-R00 are transferred to register pair R1n-R0n. The program memory consists of 10 bits and has the following state after the transfer to the register.
Program memory b9 b7 b6 b5 b4 @R0 b8 b3 b2 b1 b0
b9
b7
b6
b5
b4
b8
b3
b2
b1
b0
R1n
R0n
The high-order 2 bits of the program memory address is specified with the control register (P13).
Data Sheet U14380EJ2V0DS00
41
PD64A, 65
9.7 Branch Instructions
The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as follows.
PD64A (ROM: 1K steps) PD65 (ROM: 2K steps)
: page 0 : pages 0, 1
PD6P5 (PROM: 2K steps) : pages 0, 1
JMP addr <1> Instruction code : page 0 <2> Cycle count <3> Function a0). JC addr <1> Instruction code : page 0 <2> Cycle count <3> Function :1 : if CY = 1 PC addr else PC PC + 2
0110010001 0100010001
; page 1
0100110001
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
:1 : PC addr
The 10 bits (PC9-0) of the program counter are replaced directly by the specified address addr (a9 to
; page 1
0101010001
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
If the carry flag CY is set (to 1), a jump is made to the address specified with addr (a9 to a0). JNC addr <1> Instruction code : page 0 <2> Cycle count <3> Function :1 : if CY = 0 PC addr else PC PC + 2
0110110001
; page 1
0101110001
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
If the carry flag CY is cleared (to 0), a jump is made to the address specified with addr (a9 to a0). JF addr <1> Instruction code : page 0 <2> Cycle count <3> Function :1 : if F=1 PC addr else PC PC + 2
0111010001
; page 1
1000010001
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
If the status flag F is set (to 1), a jump is made to the address specified with addr (a9 to a0). JNF addr <1> Instruction code : page 0 <2> Cycle count <3> Function :1 : if F=0 PC addr else PC PC + 2
0111110001
; page 1
1000110001
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
If the status flag F is cleared (to 0), a jump is made to the address specified with addr (a9 to a0).
42
Data Sheet U14380EJ2V0DS00
PD64A, 65
9.8 Subroutine Instructions
The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as follows.
PD64A (ROM: 1K steps) PD65 (ROM: 2K steps)
: page 0 : pages 0, 1
PD6P5 (PROM: 2K steps) : pages 0, 1
CALL addr <1> Instruction code :
0 011010010
page 0 <2> Cycle count <3> Function :2
0100010001
; page 1
0100110001
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
: SP SP + 1 ASR PC PC addr
Increments (+1) the stack pointer value and saves the program counter value in the address stack register. Then, enters the address specified with the operand addr (a9 to a0) into the program counter. If a carry is generated when the stack pointer value is incremented (+1), an internal reset takes effect. RET <1> Instruction code : <2> Cycle count <3> Function
0 100010010
:1 : PC ASR SP SP - 1
Restores the value saved in the address stack register to the program counter. Then, decrements (-1) the stack pointer. If a borrow is generated when the stack pointer value is decremented (-1), an internal reset takes effect.
Data Sheet U14380EJ2V0DS00
43
PD64A, 65
9.9 Timer Operation Instructions
MOV A, T0 MOV A, T1 <1> Instruction code : <2> Cycle count <3> Function
1 1 1 1 0/1 1 1 1 1 1
:1 : (A) (Tn) CY 0 n = 0, 1
The timer Tn contents are transferred to the accumulator. T1 corresponds to (t9, t8, t7, t6); T0 corresponds to (t5, t4, t3, t2).
T t9 t8 T1 t7 t6 t5 t4 T0 t3 t2 t1 t0
MOV T, #data10 Can be set with MOV T, @R0
MOV T0, A MOV T1, A <1> Instruction code : <2> Cycle count <3> Function
0 0 1 0 0/1 1 1 1 1 1
:1 : (Tn) (A) n = 0, 1
The accumulator contents are transferred to the timer register Tn. T1 corresponds to (t9, t8, t7, t6); T0 corresponds to (t5, t4, t3, t2). After executing this instruction, if data is transferred to T1, t1 becomes 0; if data is transferred to T0, t0 becomes 0. MOV T, #data10 <1> Instruction code : <2> Cycle count <3> Function
0 011011111 t1 t9 t8 t7 t6 t0 t5 t4 t3 t2
:1 : (T) data10
The immediate data is transferred to the timer register T (t9-t0). Remark The timer time is set with (set value + 1) x 64/fX or 128/fX.
44
Data Sheet U14380EJ2V0DS00
PD64A, 65
MOV T, @R0 <1> Instruction code : <2> Cycle count <3> Function
0 011111111
:1 : (T) ((P13), (R0))
Transfers the program memory contents to the timer register T (t9 to t0) specified with the control register P13 and the register pair R10-R00. The program memory, which consists of 10 bits, is placed in the following state after the transfer to the register.
Program memory t1 t9 t8 t7 t6 @R0 t0 t5 t4 t3 t2
Timer T
t9
t8 T1
t7
t6
t5
t4 T0
t3
t2
t1
t0
The high-order 2 bits of the program memory address are specified with the control register (P13). Caution When setting a timer value in the program memory, ensure to use the DT directive.
9.10 Others
HALT #data4 <1> Instruction code : : <2> Cycle count <3> Function
0 001010001 0 0 0 0 0 0 d3 d2 d1 d0
:1 : Sandby mode
Places the CPU in standby mode. The condition for having the standby mode (HALT/STOP mode) canceled is specified with the immediate data. STTS R0n <1> Instruction code : <2> Cycle count <3> Function
0 0 0 1 1 0 R3 R2 R1 R0
:1 : if statuses match else F0 F1 n = 0 to F
Compares the S0, S1, KI/O, KI, and TIMER statuses with the register R0n contents. If at least one of the statuses coincides with the bits that have been set, the status flag F is set (to 1). If none of them coincide, the status flag F is cleared (to 0).
Data Sheet U14380EJ2V0DS00
45
PD64A, 65
STTS #data4 <1> Instruction code : : <2> Cycle count <3> Function
0 001110001 0 0 0 0 0 0 d3 d2 d1 d0
:1 : if statuses match else F0 F1
Compares the S0, S1, KI/O, KI, and TIMER statuses with the immediate data contents. If at least one of the statuses coincides with the bits that have been set, the status flag F is set (to 1). If none of them coincide, the status flag F is cleared (to 0). SCAF (Set Carry If ACC = FH) <1> Instruction code : <2> Cycle count <3> Function
1 101010011
:1 : if A = 0FH CY 1 else CY 0
Sets the carry flag CY (to 1) if the accumulator contents are FH. The accumulator values after executing the SCAF instruction are as follows:
Accumulator Value Before execution xxx0 xx01 x011 0111 1111 After execution 0000 0001 0011 0111 1111 0 (clear) 0 (clear) 0 (clear) 0 (clear) 1 (set)
Carry Flag
Remark NOP
x: don't care
<1> Instruction code : <2> Cycle count <3> Function No operation
0 000000000
:1 : PC PC + 1
46
Data Sheet U14380EJ2V0DS00
PD64A, 65
10. ASSEMBLER RESERVED WORDS 10.1 Mask Option Directives
When creating the PD64A and 65 program, it is necessary to use a mask option directive in the assembler's source program. 10.1.1 OPTION and ENDOP directives From the OPTION directive on to the ENDOP directive are called the mask option definition block. The format of the mask option definition block is as follows: Format Symbol field [Label:] Mnemonic field OPTION : : ENDOP 10.1.2 Mask option definition directive The directive that can be used in the mask option definition block is listed in Table 10-1. The mask option definition can only be specified as follows. Be sure to specify the following directive. Example Symbol field Mnemonic field OPTION USEPOC ENDOP Table 10-1. Mask Option Definition Directive
PRO File Address value POC USEPOC (POC circuit incorporated) 2044H Data value 01
Operand field
Comment field [; Comment]
Operand field
Comment field ; POC circuit incorporated
Name
Mask Option Definition Directive
Data Sheet U14380EJ2V0DS00
47
PD64A, 65
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25 C)
Parameter Power supply voltage Input voltage Output voltage High-level output current Symbol VDD VI VO IOHNote REM Peak value rms LED Peak value rms One KI/O pin Peak value rms Total of LED and KI/O pins IOL Note Peak value rms Low-level output current REM Peak value rms LED Peak value rms Operating ambient temperature Storage temperature TA Tstg KI/O, KI, S0, S1, S2 Test Conditions Rating -0.3 to +3.8 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -30 -20 -7.5 -5 -13.5 -9 -18 -12 7.5 5 7.5 5 -40 to +85 -65 to +150 Unit V V V mA mA mA mA mA mA mA mA mA mA mA mA C C
Note Work out the rms with: [rms] = [Peak value] x Duty. Caution Product quality may suffer if the absolute rating is exceeded for any parameter, even momentarily. In other words, an absolute maxumum rating is a value at which the possibility of psysical damage to the product cannnot be ruled out. Care must therefore be taken to ensure that the these ratings are not exceeded during use of the product. Recommended Power Supply Voltage Range (TA = -40 to +85 C)
Parameter Power supply voltage Symbol VDD Test Conditions fX = 2.4 to 8 MHz MIN. 2.0 TYP. 3.0 MAX. 3.6 Unit V
48
Data Sheet U14380EJ2V0DS00
PD64A, 65
DC Characteristics (TA = -40 to +85 C, VDD = 2.0 to 3.6 V)
Parameter High-level input voltage Symbol VIH1 VIH2 VIH3 Low-level input voltage VIL1 VIL2 VIL3 High-level input leakage current ILH2 Low-level input leakage current IUL1 IUL2 IUL3 High-level output voltage Low-level output voltage VOH1 VOL1 VOL2 High-level output current IOH1 IOH2 Low-level output current IOL1 ILH1 S2 KI/O KI, S0, S1 S2 KI/O KI, S0, S1 KI VI = VDD, pull-down resistor not incorporated S0, S1, S2 VI = VDD, pull-down resistor not incorporated KI KI/O VI = 0 V VI = 0 V Test Conditions MIN. 0.8 VDD 0.7 VDD 0.65 VDD 0 0 0 TYP. MAX. VDD VDD VDD 0.2 VDD 0.3 VDD 0.15 VDD 3 3 -3 -3 -3 IOH = -0.3 mA IOL = 0.3 mA IOL = 15 A VDD = 3.0 V, VOH = 1.0 V VDD = 3.0 V, VOH = 2.2 V VDD = 3.0 V, VOL = 0.4 V VDD = 3.0 V, VOL = 2.2 V Built-in pull-down resistor R1 R2 Data hold power supply voltage Supply current VDDOR IDD1 KI, S0, S1, S2 KI/O In STOP mode OPERATING mode IDD2 HALT mode fX = 8.0 MHz, VDD = 3 V 10 % fX = 4.0 MHz, VDD = 3 V 10 % fX = 8.0 MHz, VDD = 3 V 10 % fX = 4.0 MHz, VDD = 3 V 10 % IDD3 STOP mode VDD = 3 V 10 % VDD = 3 V 10 %, TA = 25 C -5 -2.5 30 100 75 130 0.9 0.8 0.7 0.75 0.65 1.9 1.9 -12 -7 70 390 150 250 300 500 3.6 1.6 1.4 1.5 1.3 9.0 5.0 0.8 VDD 0.3 0.4 Unit V V V V V V
A A A A A
V V V mA mA
S0, S1, S2 VI = 0 V REM, LED, KI/O REM, LED KI/O REM KI/O KI/O
A A
k k V mA mA mA mA
A A
Data Sheet U14380EJ2V0DS00
49
PD64A, 65
AC Characteristics (TA = -40 to +85 C, VDD = 2.0 to 3.6 V)
Parameter Command execution time KI, S0, S1, S2 high-level width Symbol tCY tH When releasing STANDBY mode In HALT mode In STOP mode Test Conditions MIN. 7.9 10 10 Note TYP. MAX. 27 Unit
s s s s
Note 10 + 52/fX + oscillation growth time Remark tCY = 64/fX (fX: System clock oscillator frequency) POC Circuit (TA = -40 to +85 C)
Parameter POC-detected voltageNote Symbol VPOC Test Conditions MIN. TYP. 1.85 MAX. 2.0 Unit V
Note Refers to the voltage with which the POC circuit cancels an internal reset. If VPOC < VDD, the internal reset is released. From the time of VPOC VDD until the internal reset takes effect, lag of up to 1 ms occurs. When the period of VPOC VDD lasts less than 1 ms, the internal reset may not take effect. System Clock Oscillation Circuit Characteristics (TA = -40 to +85 C, VDD = 2.0 to 3.6 V)
Parameter Oscillator frequency (ceramic resonator) Symbol fX Test Conditions MIN. 2.4 TYP. 3.64 MAX. 8.0 Unit MHz
50
Data Sheet U14380EJ2V0DS00
PD64A, 65
Recommended Ceramic Resonator (TA = -40 to +85 C)
Frequency Recommended Constant (MHz) C1 [pF] C2 [pF] 3.52 3.58 3.64 3.84 4.0 6.0 8.0 2.5 100 100 Unnecessary (C-containing type) Power Supply Voltage [V] MIN. 2.0 MAX. 3.6
Manufacturer (Order Disregarded) TDK Corp.
Part Number
Remark
FCR3.52MC5 FCR3.58MC5 FCR3.64MC5 FCR3.84MC5 FCR4.0MC5 FCR6.0MC5 FCR8.0MC5
Murata Mfg. Co., Ltd
CSA2.50MG040 CST2.50MG040
Unnecessary (C-containing type) 3.52 30 30
CSA3.52MG CST3.52MGW CSTS0352MG03 CSA3.58MG CST3.58MGW CST0358MG03 CSA3.64MG CST3.64MGW CSTS0364MG03 CSA3.84MG CST3.84MGW CST0384MG03 CSA4.00MG CST4.00MGW CSTS0400MG03 CSA6.00MG CST6.00MGW CSTS0600MG03 CSA8.00MTZ CST8.00MTW CSTS0800MG03
Unnecessary (C-containing type) 3.58 30 30
Unnecessary (C-containing type) 3.64 30 30
Unnecessary (C-containing type) 3.84 30 30
Unnecessary (C-containing type) 4.0 30 30
Unnecessary (C-containing type) 6.0 30 30
Unnecessary (C-containing type) 8.0 30 30
Unnecessary (C-containing type)
An external circuit example
XIN
XOUT
C1
C2
Data Sheet U14380EJ2V0DS00
51
PD64A, 65
12. CHARACTERISTIC CURVE (REFERENCE VALUES)
IDD vs VDD (fx = 4 MHz) (TA = 25 C) 1 0.9 1 0.9
Power supply current IDD [mA]
IDD vs VDD (fx = 8 MHz) (TA = 25 C)
Power supply current IDD [mA]
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.6 4 HALT mode OPERATING mode
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.6 4 HALT mode OPERATING mode
Power supply voltage VDD [V]
IOL vs VOL (REM, LED) (TA = 25 C, VDD = 3.0 V) 25
Power supply voltage VDD [V]
IOH vs VOH (REM, LED, KI/O) (TA = 25 C, VDD = 3.0 V)
- 20
High-level output current IOH [mA]
- 18 - 16 - 14 - 12 - 10 -8 -6 -4 -2 0 VDD
Low-level output current IOL [mA]
20
15
10
5
0
1
2
3
VDD - 1
VDD - 2
VDD - 3
Low-level output voltage VOL [V]
High-level output voltage VOH [V]
IOL vs VOL (KI/O) (TA = 25 C, VDD = 3.0 V) 500 450
Low-level output current IOL [ A]
400 350 300 250 200 150 100 50 0 1 2 Low-level output voltage VOL [V] 3
52
Data Sheet U14380EJ2V0DS00
PD64A, 65
13. APPLIED CIRCUIT EXAMPLE
Example of Application to System * Remote-control transmitter (48 keys; mode selection switch accommodated)
KI/O6 KI/O7 S0 + S1/LED REM VDD + XOUT XIN GND S2 Mode select switch
Note
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0 Key matrix 8 x 6 = 48 keys
Note S2 : Set this pin to disable when releasing STOP mode. * Remote-control transmitter (56 keys accommodated)
KI/O6 KI/O7 S0 + S1/LED REM VDD + XOUT XIN GND S2
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0 Key matrix 8 x 7 = 56 keys
Data Sheet U14380EJ2V0DS00
53
PD64A, 65
14. PACKAGE DRAWINGS
20 PIN PLASTIC SSOP (300 mil)
20 11
detail of lead end F G T
P E 1 A H I S 10
L U
J
N C D
NOTE
S K
M
M
B
ITEM A B C D E F G H I J K L M N P T U MILLIMETERS 6.650.15 0.475 MAX. 0.65 (T.P.) 0.24 +0.08 -0.07 0.10.05 1.30.1 1.2 8.10.2 6.10.2 1.00.2 0.170.03 0.5 0.13 0.10 3 +5 -3 0.25 0.60.15 S20MC-65-5A4-1
Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition.
Remark The dimensions and materials of the ES model are the same as those of the mass production model.
54
Data Sheet U14380EJ2V0DS00
PD64A, 65
15. RECOMMENDED SOLDERING CONDITIONS
Carry out the soldered packaging of this product under the following recommended conditions. For details of the soldering conditions, refer to information material Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than the recommended conditions, please consult one of our NEC sales representatives. Table 15-1. Soldering Conditions for Surface-Mount Type
PD64AMC-xxx-5A4 : 20-pin plastic SSOP (300 mil) PD65MC-xxx-5A4 : 20-pin plastic SSOP (300 mil)
Recommended Condition Symbol IR35-00-3 VP15-00-3 WS60-00-1 --
Soldering Method Infrared reflow VPS Wave soldering Partial heating
Soldering Condition Package peak temperature: 235 C; time: within 30 secs. max. (210 C or higher); count: no more than three times Package peak temperature: 215 C; time: 40 secs. max. (200 C or higher); count: no more than three times Solder bath temperature: 260 C max.; time: 10 secs. max.; count: once; Preliminary heat temperature: 120 C max. (Package surface temperature) Pin temperature: 300 C or less ; time: 3 secs or less (for each side of the device)
Caution Using more than one soldering method should be avoided (except in the case of partial heating).
Data Sheet U14380EJ2V0DS00
55
PD64A, 65
APPENDIX A. DEVELOPMENT TOOLS
An emulator is provided for the PD64A and 65. Hardware * Emulator (EB-65Note) It is used to emulate the PD64A and 65. Note This is a product of Naito Densei Machida Mfg. Co., Ltd. For details, consult Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Software * Assembler (AS6133) * This is a development tool for remote control transmitter software. Part Number List of AS6133
Host Machine PC-9800 series (CPU: 80386 or more) IBM PC/ATTM compatible MS-DOS (Ver. 6.0 to Ver. 6.22) PC DOSTM (Ver. 6.1 to Ver. 6.3) 3.5-inch 2HC OS MS-DOSTM (Ver. 5.0 to Ver. 6.2) Supply Medium 3.5-inch 2HD Part Number
S5A13AS6133 S7B13AS6133
Caution Although Ver.5.0 or later has a task swap function, this function cannot be used with this software.
56
Data Sheet U14380EJ2V0DS00
PD64A, 65
APPENDIX B. FUNCTIONAL COMPARISON BETWEEN PD64A, 65 AND OTHER PRODUCTS
Item ROM capacity RAM capacity Stack Key matrix Key extended input Clock frequency
PD62
512 x 10 bits 32 x 4 bits
PD62A
512 x 10 bits
PD64
1002 x 10 bits
PD64A
1002 x 10 bits
PD65
2026 x 10 bits
1 level (multiplexed with RF of RAM) 8 x 6 = 48 keys S0, S1 Ceramic oscillation Ceramic oscillation * fX = 2.4 to 8 MHz * fX = 2.4 to 8 MHz * fX = 2.4 to 4 MHz (with POC circuit) fX/64, fX/128 Writing count value * fX/8, fX/64, fX/96 (timer clock: fX/64) * fX/16, fX/128, fX/192 (timer clock: fX/128) * No carrier Synchronized with timer 16 s (fX = 4 MHz) n = 1 to F RESET input, POC * HALT mode for timer only. * STOP mode for only releasing KI (KI/O high-level output or KI/O0 high-level output) HALT instruction not executed when F = 1 POC 8 x 7 = 56 keys S0, S1, S2 Ceramic oscillation Ceramic oscillation * fX = 2.4 to 8 MHz * fX = 2.4 to 8 MHz * fX = 2.4 to 4 MHz (with POC circuit)
Timer Carrier
Clock Count start Frequency
Output start Instruction execution time "MOV Rn, @R0" instruction Standby mode Reset Release condition (HALT instruction) Relation between HALT instruction execution and status flag (F) POC circuit
* Mask option * Low level output to RESET pin on detection POC detection VPOC = 1.6 V (TYP.) VPOC = 1.85 V (TYP.) VPOC = 1.6 V (TYP.) voltage
* Provided * Generates internal reset signal on detection VPOC = 1.85 V (TYP.) None
Mask option Supply voltage
POC circuit only * VDD=1.8 to 3.6 V VDD = 2.0 to 3.6 V * VDD=2.2 to 3.6 V (with POC circuit)
* VDD=1.8 to 3.6 V VDD = 2.0 to 3.6 V * VDD=2.2 to 3.6 V (with POC circuit)
Operating temperature
* TA=-40 to +85 C * TA=-40 to +85 C * TA=-40 to +85 C TA = -40 to +85 C * TA=-20 to +70 C * TA=-20 to +70 C (with POC circuit) (with POC circuit) 20-pin plastic SSOP * 20-pin plastic SOP * 20-pin plastic SSOP 20-pin plastic SSOP
Package
One-time PROM model
PD6P4B
PD6P5Note
Note Under development
Data Sheet U14380EJ2V0DS00
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PD64A, 65
APPENDIX C. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT (in the case of NEC transmission format in command one-shot transmission mode)
Caution When using the NEC transmission format, please apply for a custom code at NEC. (1) REM output waveform (From <2> on, the output is made only when the key is kept pressed.)
REM output 58.5 to 76.5 ms <1> 108 ms
<2> 108 ms
Remark If the key is repeatedly pressed, the power consumption of the infrared light-emitting diode (LED) can be reduced by sending the reader code and the stop bit from the second time. (2) Enlarged waveform of <1>
<3> REM output 9 ms 4.5 ms Custom Code 8 bits Custom Code' 8 bits Data code 8 bits 27 ms Data Code 8 bits Stop bit 1 bit
13.5 ms Leader code
18 to 36 ms 58.5 to 76.5 ms
(3) Enlarged waveform of <3>
REM output 9 ms 13.5 ms 4.5 ms 0.56 ms 1.125 ms 2.25 ms 0 1
1
0
0
(4) Enlarged waveform of <2>
REM output 9 ms 11.25 ms Leader code 2.25 ms 0.56 ms Stop bit
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Data Sheet U14380EJ2V0DS00
PD64A, 65
(5) Carrier waveform (Enlarged waveform of each code's high period)
REM output 8.77 s 26.3 s 9 ms or 0.56 ms Carrier frequency : 38 kHz
(6) Bit array of each code
C0 C1 C2 C3 C4 C5 C6 C7 C0' C1' C2' C3' C4' C5' C6' C7' D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
= = = = = = = =
C0 C1 C2 C3 C4 C5 C6 C7 or or or or or or or or Co C1 C2 C3 C4 C5 C6 C7
Leader code
Custom code
Custom code'
Data code
Data code
Caution To prevent malfunction with other systems when receiving data in the NEC transmission format, not only fully decode (make sure to check Data Code as well) the total 32 bits of the 16-bit custom codes (Custom Code, Custom Code') and the 16-bit data codes (Data Code, Data Code) but also check to make sure that no signals are present.
Data Sheet U14380EJ2V0DS00
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PD64A, 65
[MEMO]
60
Data Sheet U14380EJ2V0DS00
PD64A, 65
[MEMO]
Data Sheet U14380EJ2V0DS00
61
PD64A, 65
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
62
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U14380EJ2V0DS00
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PD64A, 65
MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of IBM Corp.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98.8

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